The present invention relates to a semiconductor device and a method of manufacturing the same and it can be utilized suitably to a semiconductor device having a vertical transistor and a method of manufacturing the same.
For power devices, for example, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) used as a power switch for large current and high voltage, a vertical MOSFET is generally used. In the vertical MOSFET, a source electrode and a gate electrode are formed on one side (surface) and a drain electrode is formed on the other side (back surface) of a semiconductor substrate in which a drain current flows in the vertical direction of the semiconductor substrate.
In the power MOSFET, resistance during operation (on-resistance) should be as low as possible in order to suppress power consumption. Therefore, a vertical MOSFET in which the on-resistance per unit area is reduced has been developed by forming a gate electrode in a trench and forming a channel region in the vertical direction, thereby narrowing the distance between the gate electrodes to each other and increasing the density.
Further, in recent years, there have been appeared chip size packages of a surface drain terminal type in which respective terminals of a source, a gate, and a drain of a vertical MOSFET are formed on one side (surface) of a semiconductor substrate. Semiconductor devices of such CSP structure are disclosed, for example, in Japanese Unexamined Patent Application Publication No. 2002-353452, and Japanese Patent Nos. 5132977 and 4646284.